## LLVM
* LLVM Documents
1. [LLVM Doxygen](http://llvm.org/doxygen/annotated.html)
2. [LLVM Programmers Manual](http://llvm.org/docs/ProgrammersManual.html)
3. [LLVM Language Reference Manual](http://llvm.org/docs/LangRef.html)
4. [LLVM Target-Independent Code Generator](http://llvm.org/docs/CodeGenerator.html)
5. [Writing an LLVM Compiler Backend](http://llvm.org/docs/WritingAnLLVMBackend.html)
6. [TableGen Fundamentals](http://llvm.org/docs/TableGenFundamentals.html)
7. [LLVM Testing Infrastructure Guide](http://llvm.org/docs/TestingGuide.html)
8. [Extending LLVM: Adding instructions, intrinsics, types, etc.](http://llvm.org/docs/ExtendingLLVM.html)
9. [LLVM Atomic Instructions and Concurrency Guide](http://llvm.org/docs/Atomics.html)
10. [Writing an LLVM Pass](http://llvm.org/docs/WritingAnLLVMPass.html)
* Retargeting
1. [Tutorial : Building a backend in 24 hours (2009)](http://llvm.org/devmtg/2009-10/Korobeynikov_BackendTutorial.pdf)
2. [Tutorial : Building a backend in 24 hours (2012)](http://llvm.org/devmtg/2012-04-12/Slides/Workshops/Anton_Korobeynikov.pdf)
4. [CodeGen Overview and Focus on SelectionDAGs](http://llvm.org/devmtg/2008-08/Gohman_CodeGenAndSelectionDAGs.pdf)
5. [Design and Implementation of a TriCore Backend
for the LLVM Compiler Framework](http://reup.dmcs.pl/wiki/images/7/7a/Tricore-llvm-slides.pdf)
* Resources
1. [LLVM Developers' Meeting](http://llvm.org/devmtg/)
* Useful Post in llvm-dev list
1. [[LLVMdev] Understanding SelectionDAG construction](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040554.html)
2. [[LLVMdev] Data layout and Optimization](http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-April/048933.html)
3. [[LLVMdev] CodeGen instructions and patterns](http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-February/047742.html)
4. [[LLVMdev] Conceptual difference between "Unallocatable" and "Reserved" registers.](http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-April/049016.html)
5. [[LLVMdev] The meaning of SDNPHasChain](http://lists.cs.uiuc.edu/pipermail/llvmdev/2006-October/006900.html)
6. [[LLVMdev] Question about 'side-effect' and 'chain'](http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-December/027722.html)
7. [[LLVMdev] Difference between pattern and dag2dag isels](http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-August/004706.html)
8. [[LLVMdev] Question about porting LLVM - code selection without assembler feature](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-January/037594.html)
9. [[LLVMdev] Where can I find an explanation of $src1, $src2, $in, $ptr, etc.?](http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-August/033934.html)
10. [[LLVMdev] Adding a custom calling convention
](http://lists.cs.uiuc.edu/pipermail/llvmdev/2008-February/012709.html)
11. [[LLVMdev] LLVM new backend compiling/linking problem](http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-November/036367.html)
12. [[LLVMdev] Meaning of MIOperandInfo](http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-December/011664.html)
13. [[LLVMdev] Predicates and conditional execution](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-May/040319.html)
14. [[LLVMdev] AsmPrinter vs. MCAsmStreamer](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-November/045211.html)
15. [[LLVMdev] Questions of instruction target description of MSP430](http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-December/028111.html)
16. [[LLVMdev] How to bind a register variable with a given general purpose register?](http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-January/028314.html) FP_ONE
17. [[LLVMdev] The nsw story: part 1](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-November/045730.html)
18. [[LLVMdev] The nsw story: part 2](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/045775.html)
19. [[LLVMdev] The nsw story: part 3](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/045790.html)
20. [[LLVMdev] TargetExternalSymbol and TargetGlobalAddress](http://lists.cs.uiuc.edu/pipermail/llvmdev/2006-October/006968.html)
21. [[LLVMdev] Trig language-like code generator generator](http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-April/003901.html) (A brief description of LLVM instruction selection, although the post is quite old (2005).
22. [[LLVMdev] Instruction selector internals](http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-October/011037.html)
23. [[LLVMdev] VLIW Scheduling](http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-September/004800.html)
24. [[LLVMdev] RFC: Machine Instruction Bundle](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-December/045846.html)
25. [[LLVMdev] Supporting Complex Register Allocation Constraints (PBQP Allocator Status Update)](http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-September/034800.html) Two operand instructions.
26. [[LLVMdev] Fixed register operations](http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-May/031803.html)
27. [[LLVMdev] Questions of instruction target description of MSP430](http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-December/028133.html)
(isReMaterializable, implicit)
28. [[LLVMdev] Simple question on sign](http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-February/047694.html)
29. [[LLVMdev] Signedess of operands](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-April/039534.html)
30. [[LLVMdev] Some question on LLVM design](http://lists.cs.uiuc.edu/pipermail/llvmdev/2004-October/002437.html)
31. [[LLVMdev] Q about instruction pattern matching](http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-September/010815.html)
32. [[LLVMdev] Operand constraints](http://lists.cs.uiuc.edu/pipermail/llvmdev/2004-July/001384.html)
33. [[LLVMdev] How to partition registers into different RegisterClass?](http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-July/004592.html)
34. [[LLVMdev] LLVM Instruction Operands](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040454.html)
35. [[LLVMdev] Register Dependencies and Register Allocation](http://lists.cs.uiuc.edu/pipermail/llvmdev/2008-December/019001.html)(Load 4 words into 4 contiguous registers.)
36. [[LLVMdev] Question on instruction itineraries](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-August/042428.html)
37. [[LLVMdev] DAGCombiner rant](http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-January/019707.html) (Target specific operations and the DAG Combiner).
38. [[LLVMdev] EFLAGS and MVT::Glue](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-February/038120.html)
39. [[LLVMdev] How to define complicated instruction in TableGen (Direct3D shader instruction)](http://lists.cs.uiuc.edu/pipermail/llvmdev/2005-July/004640.html)
40. [[LLVMdev] Adding register allocator to LLVM](http://lists.cs.uiuc.edu/pipermail/llvmdev/2006-August/006353.html)
41. [[LLVMdev] Determining the register type of a MachineOperand](http://lists.cs.uiuc.edu/pipermail/llvmdev/2008-September/017203.html)
42. [[LLVMdev] addRequired vs addRequiredTransitive](http://lists.cs.uiuc.edu/pipermail/llvmdev/2006-October/006994.html)
43. [[LLVMdev] Where is liveness analysis pass?](http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-January/037428.html)
44. [[LLVMdev] Register Design Decision for Backend] (http://markmail.org/message/x6ibotqnxnlok7k5#query:+page:1+mid:hixkdgdj3idlna4e+state:results)
45. [[LLVMdev] Register based vector insert/extract](http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-April/008834.html)
46. [[LLVMdev] Modeling GPU vector registers, again (with my implementation)](http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-February/020138.html)
47. [[LLVMdev] Vector LLVM extension v.s. DirectX Shaders](http://lists.cs.uiuc.edu/pipermail/llvmdev/2007-April/008839.html)
* Research and Open Source Project
1. [Developer Resources From GPGPU](http://gpgpu.org/category/developer-resources)
2. [Whole-Function Vectorization](http://www.cdl.uni-saarland.de/projects/wfv/)