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Revision 75 - 2012-05-31 at 07:21:35

LLVM

LLVM Documents
Retargeting
Resources
1. LLVM Developers' Meeting
Useful Post in llvm-dev list
1. [LLVMdev] Understanding SelectionDAG construction
2. [LLVMdev] Data layout and Optimization
3. [LLVMdev] CodeGen instructions and patterns
4. [LLVMdev] Conceptual difference between "Unallocatable" and "Reserved" registers.
5. [LLVMdev] The meaning of SDNPHasChain
6. [LLVMdev] Question about 'side-effect' and 'chain'
7. [LLVMdev] Difference between pattern and dag2dag isels
8. [LLVMdev] Question about porting LLVM - code selection without assembler feature
9. [LLVMdev] Where can I find an explanation of $src1, $src2, $in, $ptr, etc.?
10. [LLVMdev] Adding a custom calling convention
11. [LLVMdev] LLVM new backend compiling/linking problem
12. [LLVMdev] Meaning of MIOperandInfo
13. [LLVMdev] Predicates and conditional execution
14. [LLVMdev] AsmPrinter vs. MCAsmStreamer
15. [LLVMdev] Questions of instruction target description of MSP430
16. [LLVMdev] How to bind a register variable with a given general purpose register? FP_ONE
17. [LLVMdev] The nsw story: part 1
18. [LLVMdev] The nsw story: part 2
19. [LLVMdev] The nsw story: part 3
20. [LLVMdev] TargetExternalSymbol and TargetGlobalAddress
21. [LLVMdev] Trig language-like code generator generator (A brief description of LLVM instruction selection, although the post is quite old (2005).
22. [LLVMdev] Instruction selector internals
23. [LLVMdev] VLIW Scheduling
24. [LLVMdev] RFC: Machine Instruction Bundle
25. [LLVMdev] Supporting Complex Register Allocation Constraints (PBQP Allocator Status Update) Two operand instructions.
26. [LLVMdev] Fixed register operations
27. [LLVMdev] Questions of instruction target description of MSP430 (isReMaterializable, implicit)
28. [LLVMdev] Simple question on sign
29. [LLVMdev] Signedess of operands
30. [LLVMdev] Some question on LLVM design
31. [LLVMdev] Q about instruction pattern matching
32. [LLVMdev] Operand constraints
33. [LLVMdev] How to partition registers into different RegisterClass?
34. [LLVMdev] LLVM Instruction Operands
35. [LLVMdev] Register Dependencies and Register Allocation(Load 4 words into 4 contiguous registers.)
36. [LLVMdev] Question on instruction itineraries
37. [LLVMdev] DAGCombiner rant (Target specific operations and the DAG Combiner).
Research and Open Source Project
1. Developer Resources From GPGPU
2. Whole-Function Vectorization

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Revision by Lei Mou, 2012-05-31

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